In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate charge or capacitance in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices.
The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, two or more layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer, with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.
However, it is difficult to obtain sufficient storage capacitance with a conventional STC capacitor as the storage electrode area is confined within the limits of its own cell area. Also, maintaining good dielectric breakdown characteristics between poly layers in the STC capacitor becomes a major concern once insulator thickness is appropriately scaled.
A paper submitted by T. Ema, et al., entitled "3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS," IEDM, Dig. Tech. Papers, pp. 592-595, 1988, herein incorporated by reference, discusses a 3-dimensional stacked capacitor fin structure.
The fin structure and its development is shown in FIG. 1, pp. 593 of the article mentioned above. The storage node is formed by two polysilicon layers, called fins, with gaps between the fins (the number of fins can be increased, but is limited by design rules used). Capacitor dielectric film surrounds the whole surface of the polysilicon fins (used for a capacitor cell plate) covering the fins and filling in the gaps. This design can be fabricated using current methods and increases storage capacitance, but it is not suitable for a deep submicron (such as 0.2 micron) design rule DRAM cell because the total thickness of several fins making up the cell plate is much larger than minimum feature size. In addition, the process flow needed to realize this fin structure requires precise alignment between two adjacent word lines and digits lines. This alignment along with the requirement to have the storage node poly overlap the storage node contact leads to a larger cell area that is not suitable for 0.2 micron design rules mentioned previously.
Also, in a paper submitted by T. Kisu et al., entitled "A Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node in STC DRAM Cell," Ext. Abst., 20th Conf. on S.S.D.M., pp. 582-584, 1988, herein incorporated by reference, discusses a double-stacked storage node (developed from a conventional STC structure) running parallel to word lines. The development of the double-stacked storage node discussed in the above article, requires two additional photomask steps to that of a conventional STC process. By referring to FIG. 1a on page 582, it can be seen that a first photomask step is needed to form a buried contact between the first storage node and the underlying substrate. A second photomask step is then required to pattern the 1st storage node. Now referring to FIG. 1b, a third photomask step is needed to provide an opening through the SiO.sub.2 and Si.sub.2 N.sub.4 dielectric layers allowing access to the 1st storage node. Then a fourth photomask step is required to pattern the 2nd storage node which connects to the 1st storage node.
The present invention further develops an existing stacked capacitor fabrication process by adding only one photolithography step to construct a three-dimensional stacked capacitor cell. The capacitor's bottom plate (or storage node plate) is running parallel to digit lines and is connected to an access transistor's active area by a is self-aligned buried contact (or node contact). Additionally, the storage node does not need to be critically aligned on the node contact which allows the manufacture of a smaller cell area for a given lithographic resolution.